Quantum-O · Evidence & filings
What is filed.What is prototyped.What is still speculative.
Deep-tech credibility is a matter of what you refuse to claim as much as what you do. This page names every load-bearing part of the Quantum-O architecture and labels it honestly.
Prototype vs. speculative
An explicit maturity matrix.
Area
Status
Note
Q-Ov1 open runtime & QASM compiler
prototyped
Live against the local simulator and hosted node tier.
Quantum SDK circuits & presets
prototyped
Public interface — algorithm library and shot-based execution.
Cryo-CMOS control tier design
in-design
Schematic and simulation stage; foundry-compatible flow selected.
SiV spin qubit + Si₃N₄ photonic bus
in-design
Patent-drafted architecture; tape-out gated on Phase 02 funding.
Majorana boundary shielding
in-design
Analytical model complete; requires measured results to promote.
Micro-cryogenic consumer package
speculative
Named as the load-bearing problem for on-device quantum. Roadmap Phase 03.
Filings & prior art
Named boundaries. No hand-waving.
The Quantum-O patent stack sits inside a specific prior-art region. We describe both the claim surface and the neighbours.
Drafted filings
- · Monolithic dual-tier hybrid spin-topological QPU
- · Photon-mediated CZ gate through Si₃N₄ micro-ring bus
- · Gaussian-derivative pulse engineering (GDPE) control
- · Consumer-adjacent micro-cryogenic packaging (in draft)
Full text available under NDA via the Invest portal after suitability review.
Prior-art neighbours
- · Superconducting transmon platforms (IBM, Google)
- · Trapped-ion platforms (IonQ, Quantinuum)
- · Photonic quantum platforms (PsiQuantum, Xanadu)
- · Neutral-atom platforms (QuEra, Pasqal)
Quantum-O's differentiator is the monolithic dual-tier package, not a new physics claim over these neighbours.